An efficient interpolation filter VLSI architecture for HEVC standard

EURASIP Journal on Advances in Signal Processing

Table 6 Comparisons between the proposed architecture and state-of-the-art designs

	[11]	[12]	[13]	[14]	[15]	[16]	[17]	[18]	Proposed architecture
Standard	HEVC	HEVC	HEVC	HEVC	HEVC	HEVC	HEVC	HEVC	HEVC
Technology (nm)	40	90	90	FPGA 65	FPGA 65	90	65	90	90
Parallelism	8×	64×	8×	8×	8×	8×	8×	8×	8×
Logic gate account	45.2k	211.693k	32.496k	5710 LUTs	5017 LUTs	28.5k^a	1183k^b	64.5k	37.2k
Power (mW)	N/A	N/A	N/A	379	89	N/A	198.6	7.9	4.7
Interpolation execution time (pixel/cycle)	2.58	N/A	0.73	N/A	8.5	N/A	5.26	0.84	13.4
Max operation frequency (MHz)	200	400	171	403	200	200	188	193	240
Throughput	QFHD @30fps	1080p @30fps	QFHD @60fps	QFHD @60fps	QFHD @30fps	QFHD @30fps	8K-UHD @30fps	QFHD @47fps	8K-UHD @78fps