Fig. 7From: Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usageThe 8-way synoptic structure with 8 VLIW units (denoted as .M1/2, .L1/2, .S1/2 and .D1/2) and register files (A31:A0 and B31:B0) of a C66 coreBack to article page