Table 1 Instructions’ features of some TI C66 operations
Instruction | Operand size (op1, op2, dst) [in number of core registers] | Delay slot latency (DS) | Possible execution units |
|---|---|---|---|
DADDSP | (2, 2, 2) | 2 | L, S |
DSUBSP | (2, 2, 2) | 2 | L, S |
CMPYSP | (2, 2, 4) | 3 | M |
STDW | (2, 0, 1) | 0 | D |
LDDW | (1, 0, 2) | 4 | D |
ADD | (1, 1, 1) | 0 | L, S, D |