Table 1 Synthesis results of pipelined and non-pipelined implementations of a 45X multiplier in the Altera Cyclone IV EP4CE115F29C7 FPGA
Pipelined | Total logic elements (LE) | Maximum frequency of operation (MHz) | Area × Time cost metric (LE/MHz) |
|---|---|---|---|
No | 31 | 285.47 | 0.1086 |
Yes | 34 | 376.08 | 0.0904 |