Dynamic configuration management of a multi-standard and multi-mode reconfigurable multi-ASIP architecture for turbo decoding

EURASIP Journal on Advances in Signal Processing

Table 3 Configuration transfer latency in nanosecond for different levels of sub-block parallelism

Level of sub-block parallelism (P)	Number of RDecASIPs	Transfer latency (in ns) (estimated with (11))
2	4	86
3	6	98
4	8	110
8	16	158
16	32	254
32	64	446