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Table 4 FPGA resource utilization and system performance for the RNS components— i.e., FCMA and reverse converter

From: An optimized two-level discrete wavelet implementation using residue number system

Resources

(n=7)

(n=10)

n=10

n=13

n=10

 

FCMA

RBC

FCMA

RBC

S-FCMA c

M-FCMA

Number of slice LUTs

234

114

335

143

731

999

348

Number of slice registers

375

148

478

187

792

1024

471

Number of occupied slices

121

55

158

57

360

524

164

Number of RAMB18E1

8

0

8

0

0

0

24

Output word length (bits)

22

0

31

0

31

40

31

Worst negative slack (ns)

7.3

7.2

7.1

7.29

7.23

7.26

7.29

Max. operating freq (MHz)

367.1

353.7

346.6

369.7

360.1

365.7

368.9

Data path delay (ns)

2.599

2.65

2.66

2.5

2.76

2.7

2.65

Estimated power (mW)a

25

3

29

3

6

7

21

Block RAM power (mW)

16

0

16

0

0

0

16

Latency (CC)b

5

6

5

5

6

6

5

  1. aThe IO power estimation is not considered
  2. bClock cycle
  3. cRewiring the input for implementing shift operations and a series of MAs. The FCMA involves the forward converters and modulo adders. “S-FCMA” is the shift-based FCMA, the one that rewires the input, and “M-FCMA” is the memory-based FCMA