Table 5 FPGA resource utilization and system performance of two-level DB2 DWT implementation with ZC706
From: An optimized two-level discrete wavelet implementation using residue number system
RNS-based | ||||||||
|---|---|---|---|---|---|---|---|---|
Resources | FIR | DA | (n=7) | (n=10) | (n=13) | |||
Full | Full | M-FCMA | S-FCMA** | Full | S-FCMA | |||
Number of slice LUTs | 92 | 1108 | 730 | 1000 | 882 | 1759 | 1261 | 2455 |
Number of slice registers | 494 | 1250 | 1007 | 1307 | 1231 | 1648 | 1643 | 2204 |
Number of occupied slices | 122 | 411 | 351 | 434 | 444 | 656 | 561 | 885 |
Number of memory | 0 | 44 | 16 | 16 | 32 | 8 | 16 | 8 |
Number of DSP | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Worst neg. slack (ns) | 7.654 | 6.01 | 6.59 | 6.87 | 4.73 | 6.6 | 6.86 | 6.2 |
Max. operating freq (MHz) | 426.3 | 250.6 | 293.3 | 316 | 189.7 | 294.4 | 318.8 | 263.2 |
Data path delay (ns) | 2.017 | 3.73 | 3.152 | 2.94 | 4.84 | 3.07 | 2.9 | 3.54 |
Estimated power (mW) | 13 | 63 | 42 | 50 | 55 | 44 | 81 | 63 |
Block RAM power (mW) | 0 | 37 | 20 | 23 | 29 | 8 | 46 | 15 |