EURASIP Journal on Advances in Signal Processing

Table 1 Chip characteristics of the proposed 2-D IDCT core

From: A low-area high-efficiency video coding inverse transform core using resource and time sharing architecture

Function	HEVC 4/8/16/32-point.
Process technology	TSMC 90-nm CMOS, 1P9M
Supply voltage	1.0 V
Max. clock frequency	250 MHz
Throughput rate	250 MPS
Core area	863 × 858 µm ²
\(\boxplus \) Gate counts	110 K
\(\boxminus \) 1-D IDCT	80 K
\(\boxminus \) TMEM	30 K
Power consumption	49 mW @ 250 MHz
\(\boxplus \) I/O pins	49 pins
\(\boxminus \) Input pins	22 pins
\(\boxminus \) Output pins	14 pins
\(\boxminus \) Power pins	13 pins

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