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Table 2 Comparison of inverse 2-D transform cores

From: A low-area high-efficiency video coding inverse transform core using resource and time sharing architecture

Method

[8]

[16]

[17]

[18]

[19]

[22]

[24]

Proposed

Technology

90 nm

0.18 µm

90 nm

0.18 µm

40 nm

0.18 µm

90 nm

90 nm

Gate count ⋆

142 K ∗

487 K

133.8 K

79 K

335 K

112 K+16 Kb

120 K

110 K

Frequency

150 MHz

300 MHz

270 MHz

125 MHz

400 MHz

110 MHz

149.35 MHz

250 MHz

Pixels/cycle

2.67

2.12

0.5

2

16

1

32

1

Throughput

400 MPS

636 MPS

135 MPS

250 MPS

6.4 GPS

110 MPS

3.5 GPS

250 MPS

Support standard

HEVC

HEVC

HEVC

HEVC

HEVC

HEVC

HEVC

HEVC

Support dimension

4/8/16/32

16/32

4/8/16/32

32

4/8/16/32

4/8/16/32

4/8/16/32

4/8/16/32

  1. ⋆ Estimate by 2-input NAND gate
  2. ∗ Estimate by 3-input NAND gate and the area excluding the on-chip memory