High performance and resource efficient FFT processor based on CORDIC algorithm

EURASIP Journal on Advances in Signal Processing

Table 2 The proposed architecture is compared with the implemented architecture

No. of points	Design scheme	Data width	No. of slices	Block RAM	DSP	Total no. of slices	Latency (clock cycles)	Throughput (samples/cycle)	Operating frequency (MHZ)
512	Wang [31]	16-bit FXP	3681	21	5	14,516	530	2	200
	Chandra [29]	12-bit FXP	33,640	0	0	12,087	249	2	200
	Changela [30]	16-bit FXP	11,302	0	0	11,302	270	2	230
	Nguyen [15]	16-bit FXP	12,109	0	0	12,109	263	2	200
	Proposed	16-bit FXP	9981	0	0	9981	190	2	275
1024	Wang [31]	16-bit FXP	8678	48	12	34,382	722	2	200
	Chandra [29]	12-bit FXP	20,035	0	0	15,168	500	2	200
	Changela [30]	16-bit FXP	13,449	0	0	13,449	527	2	230
	Nguyen [15]	16-bit FXP	15,452	0	0	15,452	520	2	200
	Proposed	16-bit FXP	12,647	0	0	12,647	363	2	275
2048	Wang [31]	16-bit FXP	9223	54	23	43,333	1452	4	200
	Chandra [29]	12-bit FXP	24,389	0	0	19,242	1100	2	200
	Changela [30]	16-bit FXP	16,273	0	0	16,273	1040	2	200
	Nguyen [15]	16-bit FXP	19,414	0	0	19,414	1033	2	200
	Proposed	16-bit FXP	16,098	0	0	16,098	784	2	275
4096	Chandra [28]	12-bit FXP	33,640	0	0	26,343	2028	2	200
	Changela [29]	16-bit FXP	20,615	0	0	20,615	2056	2	225
	Nguyen [15]	16-bit FXP	26,543	0	0	26,543	2058	2	200
	Proposed	16-bit FXP	19,757	0	0	19,757	1671	2	275