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Table 4 Design synthesis results and performance comparison

From: A reconfigurable and compact subpipelined architecture for AES encryption and decryption

Key Sizes

Frequency

(MHz)

Area

(Slices)

Clock

cycles

Throughput

(Mbps)

Throughput

(Mbps) [5]

128 bit

129

1766

88

375

215

192 bit

129

1766

104

318

180

256 bit

129

1766

120

275

156