Table 4 Processing times required for implementing the conventional DEDR and the developed POCS-regularized (SW/HW codesign-based) unified DEDR-POCS techniques (RSF and RASF).
Implementation method | Processing time [seconds] | |
|---|---|---|
| Â | RSF (per iteration) | RASF (per iteration) |
Hypothetical Full-Format Implementation(Evaluated PC-Oriented Implementation) | 5171.6 | 5655 |
Factorized Fixed-Point POCS-Regularized Implementation (PC-Oriented) | 19.70 | 20.05 |
Previous HW/SW codesign-based implementation [10] (without systolic arrays) | 7.82 | 7.985 |
Proposed HW/SW codesign-based implementation (with systolic arrays) | 2.51 | 2.56 |