- Research Article
- Open Access
A Baseband Signal Processing Scheme for Joint Data Frame Synchronization and Symbol Decoding for RFID Systems
© Y.-Y.Wang and J.-T. Chen. 2010
- Received: 25 January 2010
- Accepted: 26 April 2010
- Published: 31 May 2010
We proposed a novel Viterbi-based algorithm using jiggling substates for joint data sequence detection, symbol boundary self-calibration, and signal frame synchronization for the EPC-Global Gen-2 system. The proposed algorithm first represents the data-encoded scheme as a trellis diagram, and then, as a consequence; the data sequence estimation can be carried out through the Viterbi algorithm. Moreover, time duration of the symbol waveform is iteratively adjusted to generate two substates in the Viterbi algorithm so as to trace and calibrate the symbol boundary on the fly. Compared with conventional approaches, the proposed Viterbi-based algorithm can significantly improve the system performance in terms of data detection accuracy due to its full exploitation of the baseband signal structure combining with the developed substate technique.
- Matched Filter
- Data Symbol
- Data Detection
- Viterbi Algorithm
- Time Stage
Recent research on RFID systems mainly focuses on RF circuit design issues such as sensitivity improvement of the tag's antenna [3, 4] and long-range transmitter circuit design [5, 6]. Very few studies are aimed at the design of optimal baseband signal processing algorithms. As both antenna design and transmitter circuit realization pose major challenges in improving power efficiency, baseband signal processing that further boosts RFID system performance with high signal integrity is an interesting topic to explore. Conventional RFID interrogators use either a matched filter or an edge detector [7, 8] to detect encoded data. The matched filter (also known as the correlator) compares the received waveform with the prescribed data-encoded signals by using a set of integral and dump circuits for each symbol duration and then selects the most likely one as its decision output. On the other hand, the edge detector  uses the edge transition imposed on each data-encoded baseband signal as its decoding criterion. Assuming perfect symbol period estimation, the matched filter achieves high accuracy on data decoding at the expense of complex hardware implementation whereas the edge detector is vulnerable to noise perturbation due to its simple circuit structure.
However, during the initiation of inventory round, the low cost tag generally uses a rather simple way to estimate the symbol time period of the training signal sent by interrogator, and therefore there is inevitably symbol period bias between interrogator and tag. This bias estimates then accordingly serves as the symbol period for the tag's backscatter waveform. In addition to the over/or under-estimation of data symbol duration, the backscatter waveform may deteriorate further when passing through a multipath wireless fading channel. These two factors limit the application of conventional RFID systems to environments with low throughput and moderate data rate transmission. However, in a high data rate system with a large amount of information being organized into several signal frames, the accumulation of symbol period biases severely degrades system performance in terms of data detection reliability and signal frame synchronization. To overcome this problem, this study proposes a novel Viterbi-based [9–11] algorithm, called the jiggle-Viterbi with substate selection (JVSS) algorithm, which flexibly uses extended substates for joint symbol period compensation, data sequence estimation, and signal frame synchronization.
The proposed JVSS algorithm is applicable to systems that use structured waveforms to represent encoded data. In this paper, the FM0 baseband signal, employed in backscatter communication of the EPC-Global Generation-2 standard , is adopted as an example to illustrate the proposed algorithm. By decomposing the FM0 baseband signal on a half-cycle basis, we first represent the data-encoded FM0 baseband signal by a four-state Moore machine, and then the associated data detection in the interrogator can be carried out in a maximum likelihood sequence estimation (MLSE) manner which is practically attainable through the use of the Viterbi-based algorithm with acceptable computational complexity. To cope with the symbol period bias, the duration of the basis waveforms of the FM0 baseband signals is dynamically inflated/deflated by a prescribed step size in the execution of the proposed JVSS algorithm. This makes it possible to trace the symbol boundary on the fly. It is then possible to simultaneously confine the signal frame boundary within a single step size while performing data detection and signal frame synchronization. Compared to conventional approaches, in addition to significantly improving the accuracy of data detection, the proposed JVSS algorithm can effectively perform signal frame synchronization because it fully exploits the structure of the baseband signals of RFID systems. The proposed algorithm is therefore particularly useful in advanced RFID systems that transmit a large amount of information at a high data rate.
The rest of this paper is organized as follows. Section 2 introduces the system model of the backscatter modulation; Section 3 reviews the matched filter and the edge detector for baseband signal detection techniques of conventional RFID interrogators; Section 4 introduces the proposed JVSS algorithm for joint data sequence detection and signal frame synchronization; Section 5 presents computer simulation results to support the validity of the proposed algorithm; Section 6 summarize the paper.
The communication protocol of the EPCglobal system is classified into a physical layer (PL) and a tag identification layer (TIL). The PL includes the employed data coding scheme and modulation waveforms whereas the TIL designates the regulation required to establish the communication link between interrogator and tags. The operation of a RFID system begins with an inventory round in which fundamental parameters for the communication link, such as the symbol period and modulation scheme, are determined. Specifically, tags estimate the symbol period by measuring the temporal support of the training signal sent by the interrogator during the initiation of the inventory round. This training signal also provides the power source required by the circuit on passive tags to backscatter their reply messages via antennas. In this paper, we refer the communication mode from tags to interrogator as the backscatter mode. All information transmitted in the link is first processed by a baseband data-encoded scheme and then modulated by either the amplitude-shift keying (ASK) or the phase-shift keying (PSK). The backscatter mode of the EPCglobal system supports two types of the baseband data-encoding schemes: ( ) The FM0 baseband scheme and ( ) the Miller modulation. Both schemes employ the same baseband basis functions but have different data-encoding rules to represent the output data stream. Since the proposed JVSS algorithm is applicable to both baseband data-encoding schemes, this study uses the FM0 baseband scheme as the study case to describe the proposed JVSS algorithm.
2.1. The FM0 Baseband Signals
2.2. The Received Signal at the Interrogator
where , denotes the symbol period estimated at the tag and is the number of data bits in a signal frame. The additive noise is assumed to be a white Gaussian process with zero mean and two-side spectral density .
With a nominal symbol period , the interrogator recovers the backscatter data symbols from the receive signal. In this process, there are two key factors that dominate the accuracy of the recovered data. ( ) Since precise clock generators are generally not affordable for low-cost tags, and especially passive tags, a symbol period bias always exists between tags and the interrogator; ( ) the channel response will spread the waveform of each data symbol in time if the bandwidth of the channel is less than that of the baseband signal Specifically, the effects of these two factors become obvious in advanced systems where a large amount of data symbols is transmitted at a high data rate Consequently, without handling these two factors well, conventional RFID interrogators limit themselves to scenarios with low data rates and relatively less information being sent. The following subsection briefly reviews two conventional data detection approaches, the matched filter and the edge detector. Both of these approaches are symbol-based algorithms and are widely used in current RFID systems. The subsequent section introduces the proposed sequence-based JVSS algorithm.
where denotes the basis function estimate during time interval . Note that the integration for each correlator is taken over the nominal period , which means that the performance of the matched filter is greatly affected by the accumulated symbol period bias , . In other words, with an , the matched filter can survive only when the size of the signal frame, , is limited to yield a trivial ASPB.
The other existing RFID signal detection approach is the edge detector, which senses the occurrence of the transition edge on over each symbol time period to carry out data detection. Figure 2(a) shows that the waveform of the data-0 has a transition edge imposed at the middle point of the symbol period whereas the waveform of the data-1 remains constant. Compared to the matched filter, the edge detector is relatively easily implemented since it uses only a single integrator to sense the occurrence of the transition edge. However, the main drawback of the edge detector is its extreme sensitivity to noise perturbation, even if there is no symbol period bias.
Apparently, without handling the ASPB or the waveform distortion induced by the wireless channel, both the matched filter and the edge detector are not applicable to advanced RFID systems transmitting a large amount of information at a high data rate. To this end, by fully exploiting the structure of the FM0 basis functions, the following section proposes a maximum likelihood sequence estimation-based (MLSE-based) algorithm for joint data detection, symbol boundary self-calibration, and signal frame synchronization. This algorithm can optimally solve the stringent problems encountered by an RFID interrogator.
4.1. The Viterbi Algorithm
The Viterbi algorithm [9, 10], with practically acceptable complexity, is used to find the most likely sequence of hidden states that results in a sequence of observed events, especially in the context of Markov information sources. The algorithm makes a number of assumptions. ( ) Both the observed events and hidden events must be in a time sequence; ( ) these two sequences must be aligned, and an instance of an observed event must correspond to exactly one instance of a hidden event; ( ) computing the most likely hidden sequence up to a certain stage must depend only on both the observed event at stage and the most likely sequence at the previous stage . Obviously, all the above conditions are satisfactory to the signal sequences generated by the FM0 data encoding scheme as Figure 2(a) illustrates. The following section briefly reviews the Viterbi algorithm and then presents the JVSS algorithm as an extension of the Viterbi algorithm.
where , is the receive waveform segment during the th symbol time period and . Apparently, solving (7) through brute force exhaustive signal sequence searching is impractical due to its formidably high computational complexity, which grows exponentially with the block length . The Viterbi algorithm provides an alternative way to reduce the overall complexity by recursively updating the sequence searching metrics during its execution.
The above process is iteratively repeated until the end of the signal frame. A survival path is then decided by choosing the path contributing the largest CBM, in the final time stage. Accordingly, the data sequence can be collectively determined by tracing the causes of branches on the survival path.
Although the decoding of the FM0 signal sequences, via the Viterbi algorithm, can be carried out in the sense of the MLSE, which reaps a power gain over the conventional symbol-based approaches such as the matched filter and the edge detector. However, the presence of symbol period bias can not be alleviated by simply applying the traditional Viterbi algorithm. To solve this problem, the next subsection proposes a novel Viterbi-based algorithm that can simultaneously perform MLSE, symbol boundary compensation, and data frame synchronization using the proposed jiggling substate technology.
4.2. The Jiggle-Viterbi Algorithm with Substate Selection (JVSS)
Figure 4 also shows some updates of the DSPs and the SBIs as time proceeds. The above processes are repeated until the end of the data frame, where, with the maximal CBM, a survival path is determined, and the data sequence is then detected as in the conventional Viterbi algorithm. The final value of the SBI can then be used as the estimate of the signal frame boundary, achieving signal frame synchronization.
The overall procedures of the JVSS algorithm are summarized in Algorithm 1.
Algorithm 1: The JVSS algorithm.
and the DSP is updated by
Repeat steps 2-3 for each time stage. The survival path is the one with the maximal
tracing the survival path on the trellis diagram, whereas the final value of the SBI
is used to estimate the signal frame boundary.
Unlike the conventional Viterbi algorithm, in addition to passing the cumulative branch metrics of the survival path to next time stage, each substate of the JVSS algorithm provides the adapted symbol boundary information via the SBIs, to increase the accuracy of the succeeding CBM calculation. On the other hand, adjustable DSPs can effectively alleviate the accumulation of symbol period bias.
The proposed JVSS is a blind algorithm which requires no information about the channel response . Although the fading effect of the wireless channel may reverse the phase of the transmit signal, the FM0 data encoding scheme, which uses two opposite waveforms to represent a single data symbol, makes itself resistant to the phase reversal.
This section presents computer simulations to evaluate the performance of the proposed algorithm. Compared with the conventional matched filter and edge detector, two different scenarios, corresponding to a regular and a high data transmission rate, are employed to assess the accuracy of data detection and the signal frame synchronization capability of the JVSS algorithm. Both scenarios employ passive tags which backscatter the continuous waveform sent from the interrogator. All the computer simulations are conducted in their equivalent baseband models with the assumption of zero carrier frequency offset between tags and interrogator due to the use of backscatter communication. The prescribed tolerance of the symbol period bias is set to be ppm of the nominal symbol time period, that is, .
Example 1 (the regular data rate case).
Example 2 (the high data rate case).
This example uses almost the same scenario settings as those in Example 1 but adopts a smaller symbol period which corresponds to a frequency bandwidth of KHz. Apparently, this bandwidth is broader than the coherence bandwidth of the wireless channel. The short channel bandwidth gives rise to channel distortion, which smears the transmitted signals on their temporal supports. Shown in Figure 7 is the comparisons of BERs of the proposed JVSS algorithm, the matched filter and the edge detector, respectively. This figure shows that the proposed JVSS algorithm can not only cope with the ASPB effect but also robust to against the pulse deformation caused by the bandlimited channel. Also as shown in the figure, even in the case of small size of signal frame, the conventional approaches are seriously degraded by both the ASPB and the channel distortion.
This paper proposes a novel MLSE-based algorithm for joint signal frame synchronization and data detection in an RFID system. The proposed algorithm fully exploits the structure of the baseband signal of the EPC-Global Gen-2 standard to develop a trellis representation of the FM0 data encoding scheme which makes the realization of the Viterbi algorithm on the FM0 scheme feasible. In addition, by inflating or deflating the waveform of FM0 baseband signals, the JVSS algorithm can effectively trace the boundaries of data symbols during its execution. Computer simulations show that, compared to conventional approaches, the proposed JVSS algorithm has significantly higher accuracy in data detection, superior capabilities in signal frame synchronization and is robust against bandlimited channel distortion. With these features, we conclude that the proposed algorithm is particularly useful to RFID systems with large amount information to be sent in high transmission data rate.
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