Asynchronous analog-to-digital converter based on level-crossing sampling scheme
© Kafashan et al; licensee Springer. 2011
Received: 19 January 2011
Accepted: 23 November 2011
Published: 23 November 2011
In this paper, a new iterative algorithm is used to convert analog signals to digital (A/D) using an asynchronous A/D converter. It is a realtime system, which encodes the amplitude information of the analog signal into a time sequence. In particular, using asynchronous systems for data conversion is an effective technique in order to reduce power consumption. The decoder should recover original signal from irregular samples. If a more intelligent reconstruction technique is used for decoding, signals with higher bandwidth can be digitized. In this work, we employ delta- and sigma-delta level-crossing sampling schemes. These asynchronous A/D converters are simple to implement and have very good performance with lower power consumption.
Analog-to-digital converters have many applications in digital signal processing and communication systems. Conventional A/D converters consist of two steps: sampling operation followed by digital quantization. The noise introduced by signal distortion due to quantization decreases the A/D performance. In the literature, the performance of A/D converters is measured by the number of bits per sample and signal-to-noise ratio (SNR) [1, 2].
Uniform sampling is used for synchronous implementation where a common clock is operated in order to convert analog signals to digital values. In the sigma-delta modulator, the original signal is highly oversampled and the internal clock operates at a much higher rate than the bandwidth of the signal; however, the oversampled signal down-sampled at the last stage of A/D converter. On the other hand, most of the signals generated by temperature sensors, pressure sensors, electro-cardiograms and speech signals are almost always constant and may vary significantly for only brief moments [3, 4]. Thus, conventional converters using uniform sampling at the Nyquist rate are limited in the implemented signal bandwidth, but asynchronous converters can be used in order to decrease the internal clock rate.
Asynchronous converters can be implemented without a global clock and have interesting properties, such as low power consumption and reduction of electromagnetic interferences. A nonuniform sampling scheme is used for this aim. In this process, several reference amplitude levels are considered in the dynamic range of the input signal. A sample must be taken only when a reference level is crossed. In this case, samples are not spaced regularly, and the sampling rate depends on the input signal. In other words, when the input signal become active, the sampling rate is increased and vice verse. In the level-crossing scheme, two sets of the time instant and amplitude levels of the samples are saved. This sampling scheme is the dual of the uniform sampling, where the time instants are quantized, while the amplitudes are perfectly known [5–9].
In this paper, a new class of A/D converters based on the level-crossing scheme is investigated. Asynchronous delta- and sigma-delta modulation are analyzed in order to minimize the activity, decrease the power consumption of the converters and achieve a good SNR. The next section describe synchronous and asynchronous A/D converters in relation to the iterative decoding algorithm. In sections 3 and 4, the new contributions of this paper are presented, and finally Section 5 concludes this paper.
2 Basic principles
2.1 Synchronous A/D converter
In synchronous converters, uniform samples quantized to approximate a continuous range of values by a specific set of discrete values. The quantization process incurs loss of information in the reconstructed signal. Subsequently, the reconstructed signal may differ considerably from the original analog signal. In order to overcome this problem, we must use oversampling converters. In the oversampling converters, sampling rate is greater than Nyquist rate (fNyquist = 1/τNyquist). The ratio between the sampling rate and twice the signal bandwidth is defined as the oversampling ratio (OSR). After oversampling, the signal is subject to quantization and then low-pass filtered and finally down-sampled to or near to the Nyquist rate (known as decimation) .
The mathematics of sigma-delta A/D conversion is extremely challenging. Here, we use following difference equation to introduce an SDM scheme of order m.
In order to have a bounded sequence u, y and q must not be unrelated sequence because u is determined from y - q via (1). Therefore, Q must be such to tie q to y to control u.
2.2 Asynchronous A/D converter
There are many methods to reconstruct the original signal from nonuniform samples. Reconstruction can be performed by using the TVa method , the lagrange method  and the CFTb method . Suppose that (t k , k ϵZ) are increasing time instants of a irregular samples. Subsequently, nonuniform samples x s (t) can be written as . The sampling set should be a stable sampling set. This means that this set of samples uniquely determines signal x(t) and, for this reason, the relation should be satisfied, where C is a constant. For instance, if |t k - k τ | < (τ/4), the set is stable (τ is the Nyquist sampling rate).
If the norm of operator E satisfies ||E|| < 1, by increasing the number of iterations k, (6) approaches the inverse system Ĝ (as it is shown in (8)); therefore, x k (t) converges to xt.
In our problem concerning the signal from nonuniform samples, distortion operator of G is a interpolator and a low-pass filter. Nonuniform samples pass from an interpolator in order to uniform, and then, a low-pass filter is used to remove the high frequency of the output of the interpolator. The SNR of reconstructed signal is dependent on the order of low-pass filter. the iterative method is a good idea to improve A/D performance without using a complicated filter.
3 Asynchronous delta modulator
In an asynchronous A/D converter based on level-crossing scheme, the conversion of samples takes place whenever a reference level is crossed. The number of reference levels depends on the dynamic range of the continuous input signal. In delta level-crossing converters, difference between the input signal and the output of the converter is passed from a level-crossing sampler. In this case, the dynamic range of the input of the level-crossing sampler and, consequently, the number of reference levels is decreased. Therefore, the number of bits that are allocated to the amplitude of the input signal is reduced. The amplitude and time of each converted sample should be considered for digital transmission. The time difference between two consecutive samples is quantized instead of the time of each sample in order to prevent quantization error propagation. In asynchronous DMs, the dynamic range of the input signal should be known in order to specify the number of reference levels and determine the interval between them.
where P(Vin) and are the power of the input signal and its derivation, respectively The time difference of between consecutive samples is quantized according to the precision T c timer. It can be understood from above equation that, by decreasing the value of T c and increasing the precision of the time quantizer, the SNR of reconstructed signal will be increased.
Number of bits for reference levels versus precision of time quantizer
Timer resolution (kHz)
OSR = 2.38
OSR = 4.23
4 Asynchronous sigma-delta modulator
The asynchronous sigma-delta modulator can be implemented without any clock and can operate at low supply power because of its asynchronous design and simple corresponding circuitry. In synchronous SDM A/D converters, a high dynamic range is achieved. However, there is a large number of coarsely quantized samples. By combining the SDM with the level-crossing scheme, the number of converted samples is decreased and a high dynamic range is obtained. The modulator of this converter consists of an integrator and a level-crossing sampler in a negative feedback loop.
Number of bits for reference levels versus precision of time quantizer
Timer resolution (kHz)
OSR = 2.43
OSR = 4.34
Where, CLoad and are approximately in the range of (1-2) Picofarad and (100-200) Femtofarad, respectively. Also, f S and f clc are operating frequency of the circuit (OSR * fNyquist) and frequency of the timer clock, respectively. The right term of the above equation is the power, which is consumed by the timer clock. By comparing the operating frequency of the circuit in the synchronous and asynchronous converter with each other, it can be understand that asynchronous circuits are very effective converters in order to reduce dynamic power consumption.
SNR of reconstructed signal for asynchronous and synchronous sigma-delta modulator for different iteration numbers
Sigma-delta level crossing
OSR = 3.40
OSR = 16
OSR = 32
OSR = 64
N = 3
N = 3
N = 3
N = 3
T = 1.14 s
T = 1.23 s
T = 1.39 s
T = 6.65s
T = 7.11s
Sampling frequency (KHz)
Timer frequency (KHz)
Effective number of bits (ENOB)
Dynamic power consumption (μ W)
Delta level-crossing converter
(after 10 iterations)
(after 10 iterations)
converter (after 10 iterations)
This paper presents a new iterative algorithm to convert analog signal to digital (A/D) using an asynchronous A/D converter. In the proposed methods, converted samples are nonuniform, which decreases the number of additional samples and lead to decreasing in the power consumption. Simulation results demonstrate that the asynchronous sigma-delta modulator has better performance than the synchronous one, and its quality even can be enhanced by increasing the timer resolution.
The iterative algorithm is effective way to reconstruct original signal from the nonuniform samples of the asynchronous converter. Therefore, we use the iterative method to improve performance of these A/D converters and decrease the distortion caused by the SDM modulator. Hence, we can exploit filters with lower degree in order to decrease the cost and complexity of the A/D converter.
These A/D converters have many applications because of their simple structure and low power consumption. Implementation of the iterative algorithm is simple, and it is unnecessary to change the configuration of the A/D converter in order to increase the number of iterations. Also, it must be mentioned that using the iterative algorithm to improve the performance of the system supports all types of SDMs with different orders and different numbers of quantization bits.
aTime Varying. bCompound Fourier Transform.
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