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Analysis and performance of coded symbol recovery loop using oversampling
 Giuseppe Visalli^{1}Email authorView ORCID ID profile
https://doi.org/10.1186/s1363401906237
© The Author(s) 2019
 Received: 17 December 2018
 Accepted: 8 April 2019
 Published: 27 April 2019
Abstract
In this work, we propose a closedloop analog system to detect the source information of a binary data stream coded by a flexible finite automaton. We initially consider the dual sideband suppressedcarrier modulation of a base band binary amplitude waveform. The automaton introduces a symbol redundancy as phase contribution of the modulated signal by a simple mapping scheme. The proposed recovery system performs a coherent demodulation, presenting the baseband binary wave to a maximum likelihood hard detector, a simple analog trigger that estimates the source data within the symbol period. This wave is oversampled, and the final decision comes by counting the positive samples and a majority vote. We prove our approach is valid answering the most important concerns: the stability of the closed loop, a first analytical expression of the error rate when a Markov birth process models the counting phase, and finally the role of this last loop to lower the bit error rate compared to a simple Costas loop. The analysis continues by solving the problem of carrier and symbol rate recovery and the impact of nonlinearity and noise in the basic analog blocks. Behavioral simulations describe a competitive scenario in terms of error rate, comparing the proposed approach to the Costas Loop and the basic convolutional decoding strategies based on Viterbi algorithm both in the hard (Hamming metrics) and soft (Euclidean metrics) versions.
Keywords
 Closed loop system
 Decoding
 Error analysis
 Finite automata’s theory
 Stability analysis
 Viterbi algorithm
1 Introduction
The need for efficient utilization of the radio channel under additive and multiplicative noise sources has stimulated the investigation of advanced digital modulations and coding techniques. Because highly stable oscillators are available for practical applications, it has been possible to detect digital phasemodulated signals, and in these 60 years, there are many developed communication systems with such modulation. Furthermore, coding theory increases the errorcorrecting capability of transmitted information by symbol redundancy, requiring more bandwidth for the complete demodulation and decoding [1]. Maximum likelihood (ML) and maximum a posteriori probability (MAP) [2] detection methods require the loglikelihood ratio (LLR) computation, which is hardware expensive for energyconstrained applications [3]. The problem of area reduction in electronic systems concerns about cost of silicon wafers, and therefore, it has an economic impact. Instead, lowpower dissipation affects the prolonging of system lifetime of batteryoperated devices such as wireless sensor networks, implantable devices, radio frequency identification, and much more. However, lowpower CMOS and radio frequency (RF) design is not exclusively for portable systems; today, reducing power dissipation in electronic circuits is a mandatory target in consumer, industrial, space, and military applications [4].
The relative simple characterization of a digital communication system is an important advantage over analog communication, where there are many more ways to degrade a transmission. Analog decoding systems have gained many interests in the research community since the contributions by Hagenauer [5] and Loeliger et. al [6]. The main advantages are the extremely lowpower dissipation and a faster ML algorithm execution up to 1000 times than a common digital signal processor (DSP). This approach uses bipolar transistors and diodes, which realize the exponential and logarithmic function respectively [7]. These basic components calculate the loglikelihood ratio as a main operation in the detection theory. There are in the recent literature some industrial applications [8–10] that uses the analog decoder, although process variability and device mismatches are the most important drawbacks that affect the precision of LLR estimation [11].
The variable M represents the mapping order as the number of allowed symmetric phases. The automaton has rate 1/R such that M=2^{R}. The proposed recovery loop receives the signal (1) corrupted by a passband additive white Gaussian noise (AWGN) [19]. A proper coherent demodulation by a multiphase voltagecontrolled oscillator (MPVCO), a mixer, and finally a loop filter applies to a simple ML hard detector (e.g., a trigger [20]), the amplitude signal corrupted by a baseband additive white Gaussian noise. The trigger’s output is an analog estimation within the current symbol interval [kT,(k+1)T]. Finally, the decoded source symbol is chosen collecting the positive samples at rate T/S where S is generally a power of two; the current output is 1 if the counter is greater than or equal to S/2 otherwise 0.
The loop’s role is to electrically remove the cosine in (1), so it is composed by a mixer, an MPVCO at frequency f_{0} and initial phase θ_{v}, a loop filter with Laplace function H(s), and a copy of the used finite automaton to generate the current estimated phase \(\hat {\theta }_{k}\left (t\right)\). Since finite automata are discretetime linear timeinvariant (LTI) systems, it is impossible to track the current phase in the analog domain. We solve this apparent problem by using a hybrid finite automaton [21], where the output network works in the continuous time domain, receiving the source symbol’s analog estimation and tracking the current code word. The internal state update network works in the discretetime domain, receiving the final estimation at the current time step, preparing the hardware to decode the next symbol.
We analyze the Costas loop as our reference approach, completed internally by a mechanism of triggering, sampling, and finally a majority vote. We include also the Viterbi algorithms of a Mary phase shift keying (MPSK) modulation and a convolutional encoder as additional benchmarks. We use the SystemC/SystemCAMS class library to model these systems in the scenario of a pointtopoint link over AWGN channel. The loop’s bit error rate (BER) is better than our reference system working with perfect phase and timing recovery. Next, we simulate the recovery loop when the carrier’s initial phase and the timing reference introduce a jitter. After, we include the effects of nonlinearity, in the mixer and the phase noise [22] in the MPVCO. Typical architectures of highfrequency MPVCO use a closed loop of elementary voltagecontrolled oscillator (VCO) as shown in the contributions [23] and [24].
The paper has this organization. We analyze in depth the behavior and the necessary conditions for the complete feasibility of our solution in Section 2. We illustrate in details the structure and the behavior of our solution. Section 3 tackles the noiseless stability of the closed loop, followed by a first analytical expression of the bit error rate in Section 4, this last when a Markov chain models the counting process. Section 5 addresses the problem of phase and timing recovery. Section 6 shows our conducted simulations. Finally, we consider the singlesideband suppressedcarrier amplitude modulation (SSBSC AM), which introduces ideally a spectrum efficiency of 100%. Our conclusions underline the importance of this approach and a consideration of the main telecommunication problems as future directions.
2 Proposed implementation method

Q is a finite set of states.

Σ is the alphabet.

δ is the transition function where: δ:Q×Σ→Q.

q_{0} the initial state q_{0}∈Q.

F is the set of final states (F⊆Q).

Ois a finite set of symbols called the output alphabet.

X is the output transition function: X:Q×Σ→O.
When the differential phase is in the interval [ π/2, 3π/2], the cosine is negative so the wrong decision event improves its probability. This simple issue suggests an implementation of the automaton output function X, avoiding the cosine negative. The choice (7) satisfies this criterion under the hypothesis the two automata (in the transmitter and the recovery loop) have the same internal state. We see later the cosine positive matches the loop’s noiseless stability criterion. The sample and hold (S/H) samples the analog estimation (8) at rate T/S. Finally, a log_{2}(S) binary counter counts the positive samples, and a final decision \(\hat {u}_{k}\) is majority votebased. This theory applies to a binary and identically distributed source symbols. An important point, Viterbi decoders deliver the outputestimated source symbol with a delay proportional to the depth of traceback path; the proposed recovery loop estimates the source symbol always with one symbol delay (T).
3 The noiseless stability analysis
The recovery loop with two symmetrical phases (M = 2) has the wrong detection as an additional equilibrium point. If our loop supports four symmetric phases (M = 4), the stability point zero is not an additional equilibrium point for this switching system. However, this choice implies the highest outoflock probability responsible of an unaccetable global error rate. So, M = 8 is the minimum for the concrete deployment of our solution.
4 The lower bound analytical bit error rate

E0 is loop inlock and source symbol positive.

E1 is loop outlock and source symbol positive.

E2 is loop inlock and source symbol negative.

E3 is loop outlock and source symbol negative.
This error rate assumes the used finite automata aligned at current discrete time step; for this reason, we expect the proposed number is a lower bound. The use of four symmetric phase (M = 4) makes the highest value of probability (16) to 0.5. Additionally, M = 4 influences the inlock probability in (17) and the profile of the four birth rates showed in (18). Globally, the statistical effects of M = 4, although there are no oscillations in the noiseless switched system, are the highest bit error rate.
5 Phase and timing recovery
At the end of the pilot sequence, the phase θ_{A} achieves the carrier recovery: θ_{A}=θ_{0}−θ_{v}.
6 Results and discussion
We prove the validity of our assumption, simulating the proposed decoder by a mathematical description using System C/System CAMS C + + library. Assuming no intersymbol interference and perfect knowledge of carrier frequency and symbol timing, carrier frequency is f_{0}=400 Mhz, E_{s}=1 J and the symbol rate is T=80 ns; LNA bandwidth is B=2 Mhz, and the loop filter cutoff frequency is f_{p}=20 Mhz.
6.1 Error rate comparing the proposed recovery loop with known digital and analog approaches
6.2 Performance estimation using the lower bound
Lower bound BER as the sum of two contributions varying M. SNR = 0 dB
M  PL  P1  P2  BER 

Costas  1.0  0.0057  0.00  0.0057 
2  0.99  3.90e −6  0.0032  0.0032 
4  0.98  3.90e −6  0.0060  0.0060 
8  0.86  3.42e −6  1.21e −4  1.24e −4 
16  0.62  2.49e −6  6.99e −6  9.48e −6 
32  0.53  2.11e −6  2.76e −6  4.88e −6 
∞  0.50  1.98e −6  1.98e −6  3.97e −6 
SNR is 0 dB and the term P2 dominates the lower bound BER when using our recovery loop. Instead, P1 is higher in the Costas loop, since the signaltonoise ratio is aligned to a BPSK modulation.
6.3 Effects of phase and clock jitter
6.4 Effects of nonlinearity and noise in the critical blocks
6.5 Use of SSBSC AM modulation
In this last equation, the variable a is time variant and the function h(t) is the impulse response of the IIR filter used to approximate the Hilbert function. However, an highorder phase mapping (M≫1) achieves the quasistability of the equivalent dual sideband model.
7 Conclusion and future directions
In this work, we propose a coded symbol data recovery loop in a radio transmission environment over Gaussian additive noise with the minimal hardware. The analysis with the maximumlikelihood detection theory should require a complex system implementation with an analogtodigital converter and fixedprecision digital logic. Our proposed system is in a middle way between a pure analog decoder and a coded symbol recovery loop. It differs from the known decoder since it does not need the LLR computation. Finally, this approach is different from known literature on data recovery loop using oversampling since the application of actual stateofart is in digital modulations over serial links. We show in the document how the proposed approach requires the proper selection of the supported modulation and coding scheme. In particular, the use of a rate 1/R encoder limits the loop state to two possible values: inlock and outoflock. Applying the proposed approach to a simple modulation without symbol redundancy, the recovery loop ideally introduces M different loop states, so the stability condition as the correct decoding with a unique equilibrium point is difficult to achieve. Analysis of theoretical and simulated BER justifies the superior performance of our proposed system with respect to considered Costas’ recovery circuit. SNR gain using our loop with respect to the Costas approach is 2.5 dB when error rate is around 10^{−4}. The proposed approaches, based on closed and open (Costas) loop have execution time that depends on the maximum symbol frequency, which is technology dependent. Instead, the ML algorithm computation in DSP and Viterbi decoders requires an execution time that depends on technology and very largescale integration system (VLSI) architecture (e.g., parallelism). Future directions concern the application to the most important communications problems: coding, wireless channels, channel estimation, modulations, and multiple access systems.
Declarations
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